Matrix Unit Cell Scheduler (MUCS) for Input-Bu ered ATM Switches

This paper presents a novel matrix unit cell scheduler (MUCS) for input-bu ered ATM switches. The MUCS concept originates from a heuristic strategy that leads to an optimal solution for cell scheduling. Numerical analysis indicates that input-bu ered ATM switches scheduled by MUCS can utilize nearly 100% of the available link bandwidth. A transistor-level MUCS circuit has been designed and veri ed using HSPICE. The circuit features a regular structure, minimal interconnects, and a low transistor count. HSPICE simulation indicates that using 2 m CMOS technology, the MUCS circuit can operate at clock frequency of 100 MHz.